Lab V will be on 19.12.2022-22.12.2022
Group B need to check the latest version of the LabV manual. Group A will have another chance for implementation on LabVI session.
Students that have excuse to attend for the make up lab need to come to either one of the groups this week (19.12 or 22.12).
Lab V will be on 05.12.2022 - 08.12.2022 12.12.2022-15.12.2022
Lab Manual : Lab V
Group B need to check the latest version of the LabV manual. Group A will have another chance for implementation on LabVI session.
Lab IV will be on 28.11.2022 - 01.12.2022)
Lab Manual : Lab IV
There will be no task given during the lab session.
Students can attend to the lab session only if they have completed the lab manual.
Students will implement the design in the FPGA board and show it to the lab assistant.
Lab III will be on the following week (7.11.2022 - 10.11.2022)
Lab II will be on the following week (31.10.2022 - 03.11.2022)
Lab Documents : Doc
Lab I will be on the following week (17.10.2022 - 21.10.2022)
--- POSTPONED to 24.10.2022 - 28.10.2022 week---
Lab Manual : Lab I
Schematic design will be used for the Lab I.
HDL will be used for the following labs.
Microprocessors Lab will be used for the sessions.
You can either bring your PC or use the computers in the lab.
Xilinx ISE 14.7 will be used for the development platform. (Installation Guide)
You are expected to complete the steps on the lab manual to be able to attend the lab session.
A task will be also assigned druing the lab the lab session.
NEXYS4 DDR FPGA Board will be used for the implementation.