EEM 334 - Digital Systems II

Introduction

FPGAs

Lab hours have been set as follows:

VHDL Introduction

VHDL Design Styles

Lab 1: Introduction to Xilinx ISE Software and FPGA

• ISE Tutorial

Concurrent Signal Assignment

Self study-1: Combinational Logic Circuits

Lab 2: Introduction to VHDL

• .vhd files
• Nexys 4 DDR Resource Center
• Nexys 4 DDR Reference Manual

VHDL Operators

Lab 3: Combinational Circuit Design

Combinational Logic Circuits in Practice

Lab 4: ALU Design

Midterm 1 (Example)

Sequential Signal Assignment

Synchronous Sequential Circuit Design

Self study-2: Synchronous Sequential Circuits

VHDL Modeling Guidelines

Lab 5: Digital Clock

Synhronous Sequential Circuit Design (Cont'd)

Synhronous Sequential Circuits in Practice

Ten Commandments of Excellent Design-1

Lab 6: Rotating Squares

Synhronous Sequential Circuits in Practice (Cont'd)

FSM Circuits

Self study-3: Finite State Machines

Ten Commandments of Excellent Design-2

Midterm II (Example)

FSMD Circuits

Lab 7: Finite State Machines

Note: "Furthermore, you will show the number of detected sequences on the first two 7-segment displays.": You are asked to show the TOTAL number of detected sequences of "1101" from the reset of your circuit up to now.

FSMD Circuits Examples

Lab 8: Finite State Machines II

Hierarchical Design

Lab 9: FSMD Circuits

Final Example

GOOD LUCK IN YOUR FINALS...