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EEM 334 - Digital Systems II

Instructor: Prof.Atakan DOĞAN
Teaching Assistants:
Course Book: Pong P. Chu, RTL Hardware Design Using VHDL, Wiley, 2006.
Grading: Midterm I: 15%, Midterm II: 20%, Lab: 25%, Final: 40%
Other Resources: Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley, 2008.
Course Outline:
1. Week

2. Week

3. Week

4. Week

5. Week

6. Week

Midterm 1 (Example)


7. Week

8. Week

9. Week

10. Week

Midterm II (Example)


11. Week

FSMD Circuits

Lab 7: Finite State Machines

Note: "Furthermore, you will show the number of detected sequences on the first two 7-segment displays.": You are asked to show the TOTAL number of detected sequences of "1101" from the reset of your circuit up to now.


12. Week

13. Week

Hierarchical Design

Lab 9: FSMD Circuits (Updated!!!)

Final Example

GOOD LUCK IN YOUR FINALS...


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